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2013年度

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受賞

  1. 祖父江亮哉, 第158回システムLSI設計技術研究会 優秀発表学生賞, "クロック周波数向上のための動作合成におけるコントローラ設計手法" (著者: 祖父江亮哉, 原祐子, 稗田拓路, 谷口一徹, 冨山宏之), 2013年8月21日.
  2. 栗本陽介, Excellent Award, Ritsumeikan University IEEE Student Branch English Presentation Competition, 2013年10月11日.
  3. 祖父江亮哉, Challenge Award, Ritsumeikan University IEEE Student Branch English Presentation Competition, 2013年10月11日.

図書

  1. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, "Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration," Book Chapter in Embedded Systems: Design, Analysis and Verification, Gunar Schirner, Marcelo Götz, Achim Rettberg, Mauro C. Zanella, Franz J. Rammig (Eds.), pp. 171-180, Springer, June 2013.

論文誌

  1. Keita Nakajima, Shuto Kurebayashi, Yusuke Fukutsuka, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Hiroaki Takada, "Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC," International Journal on Networking and Computing, vol. 3, no. 2, pp. 217-227, July 2013. [Free Download]
  2. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda and Hiroaki Takada, "Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks," IPSJ Transactions on System LSI Design Methodology, vol. 6, pp. 122-126, Aug. 2013. [Free Download]
  3. Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama and Hiroaki Takada, "Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs," International Journal of Reconfigurable Computing, vol. 2013, Article ID 789134, 40 pages, Oct. 2013. [Free Download]
  4. Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Koji Inoue, "Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Transactions on Information and Systems, vol. E96-D, no. 10, pp. 2268-2271, Oct. 2013. [Download]
  5. Ittetsu Taniguchi, Kohei Aoki, Hiroyuki Tomiyama, Praveen Raghavan, Francky Catthoor, Masahiro Fukui, "Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path," IEICE Transactions on Fundamentals, vol. E97-A, no. 2, pp. 606-615, Feb. 2014. [Download]
  6. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda and Hiroaki Takada, "Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs," IPSJ Transactions on System LSI Design Methodology, vol. 7, pp. 37-45, Feb. 2014. [Free Download]
  7. 安藤友樹, 柴田誠也, 本田晋也, 冨山宏之, 高田広章, "SEEDS: 組込みシステム向けシステムレベル設計環境," 電子情報通信学会論文誌D, vol. J97-D, no. 3, pp. 450-460, 2014年3月.

国際会議

  1. Ryoya Sobue, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Partial Controller Retiming in High-Level Synthesis," In Proc. of Electronic System Level Synthesis Conference (ESLsyn), pp. 10-15, Austin, TX, USA, May-June 2013.
  2. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration," In Proc. of International Embedded Systems Symposium (IESS), Springer IFIP 403, pp. 171-180, Paderborn, Germany, June 2013.
  3. Hiroyuki Tomiyama, "Simulation of Many-core NoCs with QEMU and SystemC," International Forum on Embedded MPSoC and Multicore (MPSoC), Otsu, July 2013.
  4. Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "Function Profiling for Embedded Software by Utilizing QEMU and Analyzer Tool," In Proc. of International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1251-1254, Ohio, USA, Aug. 2013.
  5. Junya Kaida, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "A Static Task Mapping Algorithm with Dynamic Task Switching for Embedded Many-core SoCs," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 293-297, Samui Island, Thailand, Sep. 2013.
  6. Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama and Masahiro Fukui, "GA-based Architecture Exploration Method for Low Energy VLIW Data-Path Model," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 307-310, Samui Island, Thailand, Sep. 2013.
  7. Shunsuke Nakamura, Kohei Aoki, Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "A New Metric for Basic-Block Level Rough Energy Estimation for Power-Gated VLIW Data-Path Model," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 320-324, Samui Island, Thailand, Sep. 2013.
  8. Noriko Etani, Takuji Hieda and Hiroyuki Tomiyama, "Design, Implementation and Evaluation of Built-in Functions on Parallel Programming Model in SMYLE OpenCL," In Proc. of International Symposium on Embedded Multicore SoCs (MCSoC), pp. 113-118, Tokyo, Sep. 2013.
  9. Shunsuke Nakamura, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 354-359, Sapporo, Oct. 2013.
  10. Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi and Hiroyuki Tomiyama, "A Hardware/Software Cosimulator for Network-on-Chip," In Proc. of International SoC Design Conference (ISOCC), pp. 172-175, Busan, Korea, Nov. 2013.
  11. Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Lin Meng, "List Scheduling Strategies for Task Graphs with Data Parallelism," In Proc. of International Symposium on Computing and Networking (CANDAR), pp. 168-172, Matsuyama, Dec. 2013.

国内学会

  1. 甲斐田純也, 谷口一徹, 稗田拓路, 冨山宏之, "動的タスク切り替えを考慮した組込みメニーコアSoC向け静的タスクマッピングアルゴリズム," DAシンポジウム論文集, pp. 127-132, 下呂, 2013年8月.
  2. 栗本陽介, 福塚佑輔, 谷口一徹, 冨山宏之, "SystemCとQEMUを用いたNoCのハードウエア/ソフトウエア・シミュレータ," 電子情報通信学会VLD/DC/情報処理学会SLDM研究会, 鹿児島, 2013年11月.
  3. Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "Function-Level Profiling for Embedded Software with QEMU," 電子情報通信学会VLD/DC/情報処理学会SLDM研究会, 鹿児島, 2013年11月.
  4. Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Lin Meng, "List Scheduling Algorithms for Task Graphs with Data Parallelism," 電子情報通信学会VLD/DC/情報処理学会SLDM研究会, 鹿児島, 2013年11月.
  5. 祖父江亮哉, 原祐子, 谷口一徹, 冨山宏之, "高位合成における制御回路の構成方法の定量的評価," 電子情報通信学会VLD/DC/情報処理学会SLDM研究会, 鹿児島, 2013年11月.
  6. Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Lin Meng, "List Scheduling Strategies for Task Graphs with Data Parallelism," 第14回留日中国人研究成果報告会論文集, pp. 265-268, 大阪, 2013年11月.
  7. 田村真平, 石浦菜岐佐, 神原弘之, 冨山宏之, "CPU密結合型アクセラレータの機械語プログラムからの自動生成," 電子情報通信学会VLD/CPSY/RECONF/情報処理学会SLDM研究会, 横浜, 2014年1月.
  8. 西山直樹, 稗田拓路, 谷口一徹, 冨山宏之, "組込みメニーコア向けOpenCLプログラムの機能検証環境," 情報処理学会SLDM/EMB/電子情報通信学会CPSY/DC研究会, 石垣, 2014年3月. (SLDM研究会優秀発表学生賞)
  9. 甲斐田純也, 谷口一徹, 冨山宏之, "動的タスク切り替えを考慮した組込みメニーコアSoC向けタスクマッピング手法の拡張," 情報処理学会SLDM/EMB/電子情報通信学会CPSY/DC研究会, 石垣, 2014年3月.
  10. 祖父江亮哉, 原祐子, 谷口一徹, 冨山宏之, "高位合成におけるマルチプレクサの遅延の削減手法," 情報処理学会SLDM/EMB/電子情報通信学会CPSY/DC研究会, 石垣, 2014年3月.

その他

  1. 鯉渕道紘, 冨山宏之, "メニーコア/ネットワークオンチップの基礎と組込みシステムへの応用," 組込みシステム技術に関するサマーワークショップ(SWEST15), チュートリアル講演, 下呂, 2013年8月.
  2. Hiroyuki Tomiyama, "SMYLE OpenCL: A Parallel Programming Framework for Embedded Manycore SoCs," SNU-ESRC and Samsung-SATTI Joint Workshop, Seoul/Suwon, Korea, Sep. 2013.
  3. Ryoya Sobue, "Partial Controller Retiming in High-Level Synthesis," Ritsumeikan University IEEE Student Branch English Presentation Competition, Oct. 11, 2013. (Challenge Award)
  4. Yosuke Kurimoto, "A Hardware/Software Simulator for NoC using SystemC and QEMU," Ritsumeikan University IEEE Student Branch English Presentation Competition, Oct. 11, 2013. (Excellent Award)